1. Field of the Invention
The present invention relates to data processing with a translation state change, and more particularly, to data processing wherein a jump and translation state change operation can be performed at the same time.
2. Description of the Prior Art
In conventional computer systems, data and program instructions are stored in a memory storage that can be addressed using either a virtual address or a physical address by a running program (i.e. a process). A process in User mode accesses the memory using virtual addresses, whereas a process in Kernel mode can use virtual addresses or physical addresses. When virtual addresses are used, the virtual addresses must be translated into corresponding physical addresses to access the physical memory in the computer system. Furthermore, the virtual address to physical address mapping is completely controlled by Kernel mode processes. This way, the User mode processes cannot access the memory unless allowed by the Kernel processes. This memory address translation is supported by a hardware device called a Memory Management Unit (MMU), which allows physical memory space to be allocated dynamically. In principle, a User mode process will always have the translation state turned on (i.e. using a virtual address), while a Kernel mode process can operate either with the translation state turned on (i.e. using a virtual address) or with the translation state turned off (i.e. using a physical address). The frequent memory space access operations include fetching program instructions, and reading and writing program data.
To service an external event while a computer system is running in a User mode program, the User mode process will be interrupted by the external event and the computer system will switch into running a Kernel mode process (e.g. an external event handler) with the translation state turned on or off, depending on different usage situations. The advantages of running with translation state turned on are that data is protected from corruption, as address mapping must occur for the physical memory to be accessed; and the data space can be dynamically managed such that shortage of usable physical memory will not cause a system crash. With the translation state turned off while accessing the memory, however, there are the advantages of not consuming MMU translation resources, not relying on translation information being ready in system error or boot conditions, and increasing the memory access performance by skipping all the necessary translation steps. Since translation On/Off states have their own advantages depending on different usage conditions, the Operating System (OS), and the main Kernel mode program, may elect to run in translation On or translation Off state.
In conventional systems, when an interrupt occurs, the translation state is first updated to a pre-determined translation state value, the system waits for a confirmation of the translation state change, then jumps to the Kernel mode interrupt handling program using the new translation state. In FIG. 1, all the above-mentioned operations are encompassed in the “Interruption” transition arrow line (102) from translation On state (101) to translation Off state (103). As can be seen in FIG. 1, the pre-determined new translation state is Off.
FIG. 1 is an example flowchart of a normal interruption handling procedure in the Kernel mode program in a computer system illustrating different steps placed in two columns based on the MMU translation On and Off states according to the conventional art. The procedure includes:
Step 101: User mode program data processing, and an interrupt is received;
Step 102: Interrupt accepted by hardware, transition from User mode to Kernel mode, and transition from translation On state to translation Off state, start to fetch Kernel mode program with translation Off;
Step 103: Kernel mode program instruction fetching and data processing under the translation Off state;
Step 105: Change Translation to On state by a Kernel mode program instruction;
Step 107: Execute an instruction to wait for translation state change to complete;
Step 109: Jump to Kernel mode program that needs to operate (fetching instruction, reading/writing data) under the translation On state;
Step 113: More Kernel mode program data processing under the translation On state;
Step 115: Change Translation to Off state by a Kernel mode program instruction;
Step 117: Execute an instruction to wait for change to complete;
Step 119: Jump (return) to Kernel mode program that needs to operate (fetching instruction, reading/writing data) under translation Off state;
Step 123: More Kernel mode program data processing under translation Off state;
Step 125: Return from Kernel mode program interruption handling to the interrupted User mode program;
Step 127: Continue User mode data processing after the interruption point with translation turned on.
When the system first moves to Kernel mode program data processing (Step 103) due to an interrupt event, the Translation State is changed to Off to ease the User mode to Kernel mode transition. After certain data processing is done under the translation Off state, there is a need to perform (call) some function which is required to operate under the translation On state. Therefore, at this time, a series of conventional individual operations are performed by program instructions to complete the function call. First, an instruction is used to change the translation state from Off to On (Step 105). Then, a special instruction is executed for the hardware system to wait for a confirmation of the change (Step 107) before executing the next step (jump instruction in Step 109). The jump instruction in Step 109 does not need to operate under translation On state. However, to ensure Step 113 does operate under translation On state starting from the program instruction fetching in Step 113, the instruction in Step 107 has to be performed before the jump instruction in Step 109 since the jump instruction in Step 109 has no way to guarantee a translation On state for the instruction in Step 113.
Under the conventional method, the instructions in Step 107 and Step 109 require identity mapping (making virtual address equal to physical address in the MMU address translation unit) of their instruction addresses, as the translation state when fetching these instructions cannot be determined precisely and can be either On or Off, depending on system timing. Please note that Step 107 (and Step 117) is placed across between the translation On and the translation Off columns in FIG. 1. Making these instructions identity mapped on their instruction addresses is doable in theory, but troublesome in practice. First, this defeats the purpose of using translation Off state to save MMU translation resources; further, this can slow down the program execution if translation steps need to be performed for these instructions; and additionally, it is harder to manage memory allocation when compared with normal non-identity-mapped memory management schemes.
When returning from the function that needs to operate under the translation On state to the calling function which needs to operate under the translation Off state, a similar series of conventional instructions needs to be executed (Step 115, Step 117, and Step 119). The same instruction address identity-mapping requirement is required for the instructions in Step 117 and Step 119.